Smart Predictive Testing for Semiconductors
DOI:
https://doi.org/10.5281/zenodo.22111538Keywords:
Predictive Semiconductor Testing, AI-Enabled Test Engineering, System-on-Chip Reliability, Component Fault Prediction, Risk-Aware Test Coverage, Intelligent Test Vector Generation, Latent Defect Detection, Hardware Accelerator Validation, Multi-Core SoC Testing, Test Resource Optimization, Fault Interaction Modeling, Predictive Quality Assurance, Silicon Yield Improvement, Time-to-Market Optimization, AI-Driven Verification Frameworks, Test Prioritization Strategies, Integrated Test Architectures, Reliability Analytics, Semiconductor Manufacturing Intelligence.Abstract
Next-generation semiconductor chips require predictive testing to assure the quality, reliability, and time-to-market of increasing complex systems-on-chip with multiple processor cores and dedicated hardware accelerators. AI-enabled methodologies are needed such that the test coverage and resource commitments are commensurate with the risk of undetected latent defects.
Against this background, this work presents the architecture of a predictive testing framework that deploys AI technologies to address all main elements crucial for predictive testing—component fault prediction, test conditions that prioritize areas with elevated risk, and test vectors that consider fault interactions. Core capabilities are outlined, the integration approach specified, and the expected outcomes discussed. The proposed predictive testing framework contributes to the body of knowledge by providing AI-enabled methodologies that go beyond simple fault detection and create a predictable testing roadmap for semiconductor chips.
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Data Availability Statement
Datasets used in the study were sourced from public repositories, including data released by the National Instrument Embedded Systems Benchmark Suite, along with newly collected data from private sources. Public data are available upon request from the original repositories.
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